The left pane shows the source code. The right pane displays a diagram of the synthesized circuit. The circuit is not currently displayed at the logic gate level, though this might be added in the future.

You can drag to move and either scroll or pinch to zoom. Click to reset the zoom. Click to enter fullscreen; press escape to exit fullscreen.

If you double-click on a component, you can view its internal structure (if available). If you hover on a component or a wire, its source code will be highlighted; if you click on a component, you will jump to the source code. You can also click on a component's type if it defined in the minispec source. Hovering over a wire shows its type and source.

The latency of components is shown in green. Note that the timing for a component includes synth's optimizations for that component, but only for that component, so timings for a component will likely be shorter than suggested by the timings of its child components, especially for smaller componenets (and even when examining only the critical path). I will look in to the possibility of synthesizing module methods separately from module rules to give more detail about latencies as opposed to just the minimal clock cycle.